The present invention concerns a source voltage control circuit for use in a semiconductor memory device, and particularly a circuit for keeping a stable internal source voltage regardless of variation of an external source voltage and linearly increasing the internal source voltage when the external source voltage is equal to or greater than a specified value.
Recently, the semiconductor devices tend to be more and more highly integrated, so that in a semiconductor device of submicron order the reduction in the device area causes the corresponding increase of the voltage applied thereto, thus considerably affecting the reliability of the device.
For example, in a MOS (Metal Oxide Semiconductor) transistor much used for highly integrated semiconductor memory devices, although the external source voltage is maintained at constant value such as 5V, the channel length becomes shortened less than 1.mu.m so that the drain voltage is increased. Accordingly, there occurs the punch-through phenomenon that the depletion layer near the drain extends to the source region. This phenomenon increases the leakage current between the source and drain so as to badly affect the operation of a fine MOS transistor of submicron order.
In addition, the internal field intensity increased according to the increase of the drain voltage appears in a depletion layer near the drain, so that some of the carriers get an additional energy, thus resulting in hot carrier effect that involves change of the threshold value caused by the carriers penetrating the gate oxide layer, increase of the substrate current caused by impinging ionization, deterioration of the device, etc.
In order to prevent the reliability of the semiconductor device from being degraded by the punch-through and hot carrier effect, the source voltage of 5V presently used as the standard source voltage or external source voltage must be necessarily dropped to 3.3V.
However, because the change of the voltage level of a system is two to three years slower than the change of a memory chip area, there is required, at the intermediate stage of the change, a source voltage control circuit for dropping the external source voltage to obtain the internal source voltage.
Referring to FIG. 1 for illustrating a conventional source voltage control circuit, the circuit includes a first and second single-ended N-channel input differential amplifiers 20 and 30 respectively with external input voltages V1 and V2, a feedback circuit 40 with inputs receiving the outputs of the first and second differential amplifiers 20 and 30 and a first output applied to the other input terminals of the first and second differential amplifiers 20 and 30, and a third differential amplifier 50 with a positive input terminal connected to a first output node 47 of the feedback circuit 40 and a negative input terminal connected to the output 51 thereof.
The first and second differential amplifiers 20, 30 include first NMOS transistors 23, 34 with the gates respectively connected to the input voltages V1 and V2, second NMOS transistors 24, 33 with the gates commonly connected to the second output node 48 of the feedback circuit 40, separate current sources 25, 35 respectively connected between the sources of the first and second NMOS transistors 23 and 24, 33 and 34 and ground voltage terminal, first and second PMOS transistors 21 and 22, 31 and 32 connected to external source voltage terminal, and output nodes 26, 36 between the first PMOS transistors 21, 32 and the first NMOS transistors 23, 34.
The feedback circuit 40 includes a third and fourth PMOS transistors 41 and 42 with the channels connected between the external source voltage terminal and a first output node 47 and the gates respectively connected to the outputs of the first and second differential amplifiers 20 and 30, a first resistor 45 connected between the first output node 47 and a second output node 48 commonly connected to the gates of the second NMOS transistors 24, 33 of the first and second differential amplifiers 20 and 30, and a second resistor 46 connected between the second output node 48 and ground voltage terminal. The feedback circuit 40 produces a reference voltage Vref at the first output node 47 between the second PMOS transistors 41, 42 and the first resistor 45, and feeds back the voltage divided by the first and second resistors 45 and 46 to the other inputs of the first and second differential amplifiers 20 and 30.
The third differential amplifier 50 receives the reference voltage Vref from the feedback circuit 40 through the positive input, thus producing internal source voltage that is equal to the reference voltage Vref.
FIG. 2 is a graph for illustrating the internal source voltage against the external source voltage according to the conventional source voltage control circuit.
The horizontal axis represents the external source voltage, and the vertical axis the internal source voltage. There is shown the internal source voltage "c" according to the change of the two input voltages a and b. For descriptive convenience, the external source voltage is divided into three intervals which include the first interval 60 below 3.3V, the second interval 61 from 3.3V to 6.6V, and the third interval 62 over 6.6V.
The operation of the conventional source voltage control circuit will now be described with reference to FIGS. 1 and 2.
The first and second differential amplifiers 20 and 30 receive the externally applied voltages V1 and V2 respectively through the gates of the first NMOS transistors 23 and 34, and the voltage ##EQU1## divided by the first and second resistors 45 and 46 through the gates of the second NMOS transistors 24, 33. Thus, one of the NMOS transistors that receives more higher voltage is more turned on producing an output of "low" or "high" state at the output nodes 26, 36.
The outputs at the output nodes 26, 36 control the current pass capability of the third and fourth PMOS transistors 41, 42 so as to produce a desired reference voltage Vref at the first output node 47.
When the external source voltage is within the first interval 60 below 3.3V, one input voltage V1 of the first differential amplifier 20 is greater than one input voltage V2 of the second differential amplifier 30 as shown in FIG. 2. Accordingly, until the other input voltage ##EQU2## becomes equal to the input voltage V1, the first NMOS transistor 23 of the first differential amplifier 20 is turned on so as to turn on the third PMOS transistor 41 of the feedback circuit 40. Thus, the reference voltage Vref from the first output node 47 is increased in proportion to the externally applied source voltage.
Meanwhile, when the external source voltage is within the second interval 61 of 3.3V to 6.6V, the one input voltage V1 of the first differential amplifier 30 is greater than the one input Voltage V2 of the second differential voltage 30. Accordingly, until the other input voltage ##EQU3## of the first and second differential amplifier 20, 30 becomes equal to the one input voltage V1 of the first differential amplifier 20, the first differential amplifier 20 keeps on operating. Hence, the reference voltage Vref equals to (R1 + R2/R2).V1. In this case, because the voltage V1 is constant, the reference voltage Vref becomes to have a constant value regardless of the increase of the external source voltage. Thus, the internal source voltage Int Vcc has a constant value of 3.3V.
When the external source voltage is within the third interval 62 over 6.6V, the one input voltage V2 of the second differential amplifier 30 becomes greater than the one input voltage V1 of the first differential amplifier 20. Accordingly, until the other input voltage ##EQU4## of the first and second differential amplifier 20, 30 becomes to equal the one input voltage V2 of the second differential amplifier 30, the second differential amplifier 30 keeps on operating as the main differential amplifier. In this case, the reference voltage Vref is proportional to V2 so as to be increased with a constant slope according to the increase of V2.
As described above, it is very important to increase the internal source voltage for the reliability of a semiconductor device when the external voltage gets over a specified value (6.6V), and the limit of the internal source voltage depends on the whole characteristics of the semiconductor memory device. Hence, the slope of the internal source voltage should be readily adjusted when the external source voltage gets over a specified value.
However, in order to adjust the slope of the internal source voltage according to the conventional source voltage control circuit, it is necessary to change both of the input voltages V1 and V2 of the first and second differential amplifiers 20 and 30 and the first and second resistors 45 and 46 of the feedback circuit 40, thereby resulting in difficulty.
Further, the current consumed by the reference voltage generating circuit 10 of the conventional source voltage control circuit during the stand-by is the sum of the current flowing through the first and second resistors 45 and 46 of the feedback circuit 40 and the current resulting from the input voltages V1 and V2 of the first and second differential amplifiers 20 and 30. Hence, although the stand-by consuming current of a semiconductor memory device should be maintained very small, it becomes very large because the conventional reference voltage generating circuit itself includes a differential amplifier.